OCZ & Marvell Create Native PCIe SSD Controller, Z-Drive R5 to Debut Next Weekby Anand Lal Shimpi on January 6, 2012 9:00 AM EST
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- Z-Drive R5
Just a couple of months after launching its first SATA based SSD controller developed in-house, OCZ is announcing a PCIe based SSD controller co-developed with Marvell. The controller is based on Marvell's 88NV9145 silicon, codenamed Kilimanjaro
, and is an OCZ exclusive as the two companies apparently worked together in creating it. I'll see the chip in person next week at Storage Visions (just before CES) but it should carry both OCZ and Marvell logos. It looks like there will be an OCZ derived version of this chip as well as a Marvell branded part that will be available for others to use.
The controller itself features a native PCIe 2.0 x1 interface rather than SATA. That in itself isn't very impressive, but the first platform to use it will feature an array of these controllers behind a PCIe switch. The first implementation will be the OCZ Z-Drive R5 and will be available in MLC, eMLC and SLC NAND configurations of up to 12TB.
OCZ is claiming compatibility with VMware ESX/ESXi, Linux, Windows Server 2008 and OS X. Both full and half-height configurations will be available, similar to the Z-Drive R4.
I'm curious as to why OCZ and Marvell decided to design a native PCIe to NAND Flash controller but limited it to a x1 interface. Ideally we'd see something like a native x4, x8 or x16 controller, especially given how much bandwidth you can push through these large NAND arrays. I'll find out more next week for sure, but I wonder if the target market for this controller might be something beyond a multi-controller PCIe card.
Update: Marvell released more details about the 88NV9145 silicon. Each PCIe 2.0 x1 controller (pictured above) supports four NAND channels and up to four NAND die per channel. Using 8GB NAND die that works out to be a maximum capacity of 128GB of NAND per controller (we'd need how many controllers to hit 12TB!?). Marvell is claiming its controller is good for up to 93,000 4K random read IOs per second or 70,000 4K random write IOPS.
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kensiko - Friday, January 6, 2012 - linkLOL it's like the current Marvell SATA 6Gbps controller, it doesn't perform well at all.
r3loaded - Friday, January 6, 2012 - linkYou'd have though they'd at least use PCIe 3.0 to avail of the 1GB/s transfer speed on that single lane.
therealnickdanger - Friday, January 6, 2012 - linkI don't think this means the whole device is limited to x1. If I understand the article properly, EACH controller uses an x1 connection. Instead of have a x16 card with SATA connections to each NAND module, they could have an x16 card with 16 x1 connections to NAND modules.
"the first platform to use it will feature an array of these controllers behind a PCIe switch"
I read this to mean that there will be multiple x1 controllers working together for a single drive likely configurable to x4, x8, or even x16 arrays. If each controller addresses its own NAND before being processed in a RAID-like fashion, then this could be one beast of a device.
I could be optimistic and be projecting a little here, but anything less than that seems like a complete step backward.
therealnickdanger - Friday, January 6, 2012 - linkLooks like I was correct - completely scalable from x1 to x16:
Death666Angel - Friday, January 6, 2012 - linkThe x1 limitation is indeed strange. And I'm not in the market for such a thing anyway. But it's an interesting product and someway down the line we'll maybe see 50 to 100GB NAND on the mainboard for the OS with such a device. :-)
xdrol - Friday, January 6, 2012 - linkOne module uses 1x interface.
16 module uses 16x interface.
Death666Angel - Saturday, January 7, 2012 - linkStill seems counter intuitive to me. Why would anyone ever need X1 when that can be saturated by SATA3 already. All this does is add more PCB space and silicon cost. Why not go x4 already? Oh well, I'm no chip designer...
jjj - Friday, January 6, 2012 - linkMarvell was talking recently about PCIe based SSDs in Ultrabooks next year,maybe it's related to the x1 issue just not very sure how yet (no idea how many PCIe lines IB Ultrabooks will have.
jjj - Friday, January 6, 2012 - linkPS: next year as in this year
jjj - Friday, January 6, 2012 - linkThe Marvell press release has a bit more info http://investor.marvell.com/phoenix.zhtml?c=120802...