AMD Updates its 25x20 Goal: Progress in a Generationby Ian Cutress on September 5, 2018 9:05 AM EST
Last year we published an article detailing AMD’s progress on its self-set 25x20 goal for its processors: 25x more energy efficiency of its chips by the year 2020. In our Raven Ridge APU analysis, AMD detailed the metrics it uses to measure its success in that goal. Recently AMD updated its graphs showing that improvements in this year's devices with Raven Ridge has pushed it closer to its goal. We recap how AMD tests and what these new numbers are.
Raven Ridge 2018: Same Silicon, Better System
First, let us discuss AMD’s latest announcements. During Hot Chips in August, AMD released a new update to its 25x20 goal, showing that while moving from 2017 to 2018, they have kept the same hardware but improved efficiency. Sounds too good to be true, right?
This is the graph in question.
The base value for AMD’s goal is on its Kaveri mobile processors, which by the standards of today set a very low bar. As AMD moved to Carrizo, it implemented new power monitoring features on chip that allowed the system to offer a better distribution of power and ran closer to the true voltage needed, not wasting power. After Carrizo came Bristol Ridge, still based on the older cores, but used a new DDR4 controller as well as lower powered processors that were better optimized for efficiency.
A big leap came with Raven Ridge, with AMD combining its new highly efficient Zen x86 cores and Vega integrated graphics. This heralded a vast improvement in performance due to doubling the cores and improving the graphics, all within a similar power window as Bristol Ridge. This boosted up the important 25x20 metric and keeping it well above the ‘linear’ gain.
That was in 2017, and now in 2018 AMD is not a launching any new optimized mobile processor architectural designs, so how come Raven Ridge gets a significant boost? There are two ways.
When we talk about processor efficiency, binning the processor for the best voltage/frequency response is one way to optimize everything in one go. By choosing the best version of the silicon you can find, performance is higher, power is lower, and efficiency goes up. Because different processors can perform differently, a good binning process is required – as well as having sufficient volume to make it a retail product. As companies like AMD and the foundries understand manufacturing process, tweaks are often made to improve performance and reduce power – at the extreme this could mean optimizing one wafer for a single die. I mean, they could if they wanted.
The second is in the way how AMD calculates its 25x20 goal value. Here’s a recap of what we published last time around.
Calculating X: Get Me Some X Factor
AMD calls the value it calculates as X, defined as the ratio between a performance metric C and an efficiency metric E. In 2017, it gave detailed notes on how it calculates these values:
- Overall performance efficiency X is C divided by E
- Performance C is a 50:50 average pf CPU and GPU performance compared to Kaveri
- CPU Performance from Cinebench R15 nT Score
- GPU Performance from 3DMark 11 P Score
- Energy Use E is defined by ETEC 'Typical Energy Consumption from Notebooks' as per Energy Star Program Requirements, Rev 6.1 Oct-2014
- Kaveri is the baseline where X = 1
The secret sauce is based on how you calculate C and E. The headline equation is as stated above:
The compute metric C is relatively easy to understand. Here AMD takes the 50-50 weighted average of CPU and GPU performance with the Cinebench R15 multi-threaded test and 3D Mark 11 P full benchmark.
Using Kaveri as a base result of 1.0, Carrizo scores 1.23, Bristol Ridge scores 1.36, and Raven Ridge 2017 scored 2.47. AMD hasn’t given scores for Raven Ridge 2018, however we analyze that below.
The efficiency metric E is vastly more complicated. It relies on a ‘typical energy use’ model defined by ETEC Energy Star program that adds weights based on sleep power, idle power, and some loading power. The equation looks a little like this:
The PT(x) options are the power consumed in those modes. The main thing to bring up about this metric is that it ends up being highly dependent on the device or laptop the processor is being used in. If you want the best result, you need a device that has a low powered, preferably low resolution but efficient display, a small efficient SSD, as few controllers as possible, and as much thermal headroom as possible. The best environment becomes this odd hybrid of premium components but low specifications.
For this metric AMD uses their internal reference platform, which is often based on one of the first devices to launch with the new product. This is where we initially believe that AMD’s improvements kick in – the first devices in 2017 with Raven Ridge were, not to sugar coat it, rather middle-of-the-road. As reported by our sister website Laptop Mag, the HP Envy x360 with Raven Ridge was a repurposed chassis from HP’s catalogue, rather than something hyper optimized. It is likely that AMD’s reference design mirrors this unit a lot, as AMD and HP work very close together. But clearly room for some improvement, which is where we think this ‘Raven Ridge 2018’ metric comes in to play.
For those keeping track, again the base line for this value is referred back to Kaveri. Kaveri also sets a low bar here, being a 19W TDP processor to begin with, and Carrizo improved the metric a lot through its much more optimized power monitoring and delivery. The goal here is for a lower value, so while Kaveri scored 1.00, Carrizo was 0.35, Bristol Ridge was 0.34, and Raven Ridge was up to 0.44, but gave almost double the performance of Bristol Ridge. As always, these values are often trade-offs, so efficiency becomes an important metric.
So What is Raven Ridge 2018 Then?
In AMD’s materials, the results and specifications of this new chip are not listed. Our sister website Tom’s Hardware believes that the new numbers are based on an upcoming processor such as the Ryzen 7 2800H, which was accidentally disclosed in a to-be-announced HP-based AMD device. If this is true, then AMD has likely gone for both better binning and a better notebook for their values. It is well within the realm of possibility, although not anything we can confirm.
What we can do is interpolate AMD’s graphical results. We have all the values, so let’s do the math.
So interestingly enough, AMD’s lack of y-axis is a little bit of an obfuscation. This graph is actually a logarithmic graph, with that straight line actually a bit of an exponential curve. This is because the normal linear graph doesn’t look too great. So we have to read off a logarithmic graph to get the values. We came up with this graph:
On the logarithmic graph, the job looks almost done. The non-log plot looks like the task is not even half done:
For anyone wondering, the equation for the ‘goal’ line approximates to:
Reading off of AMD's original graph, and noting that the Raven Ridge 2018 is a few pixels more above the log-plot line than the Raven Ridge 2017 value, we get an X of around 9.7.
Now we can put it all into a single table
|AMD's 25x20 Goal: Progress|
|3DMark 11 P||Compute
|* Data Interpolated from AMD's Graph
** Value AMD should hit on current trajectory
*** Lower than originally disclosed in 2017, see below
The value of X jumping up from 5.61 in Raven Ridge 2017 to 9.70 in Raven Ridge 2018 is a very large jump, even though it does not look like much on the graph. It corresponds to a rise of 72%, which would mean that either performance has increased 72%, or the power efficiency of the device being used has improved by 72%.
As AMD has not officially given values for C, E, or X yet, we can play around with various values to score what AMD has listed on its own graph. However, because the way the number is calculated, we can make some observations.
*** When we first published about Raven Ridge 2017 last year, AMD gave it a value of 5.86x, using a Cinebench score of 719 and 3DM11P of 4315, which made C = 2.56, but the same value of E, so 2.56C/0.44E = 5.86X. We've reached out to AMD as to why they are now using lower scores for this part.
In 2018, Raven Ridge Designs Have Been Optimized
The jump from Bristol Ridge to Raven Ridge, even with the sizeable jump in Cinebench and 3DM11 results, was not that great for a new generation of parts: from 3.97x to 5.66x. For a system that offered two more physical cores and a sizeable graphics boost, it was let down by the fact that the metric for E, the denominator in the equation, increased by around 30%. In an equation with a large numerator and small denominator, minor changes in that denominator can cause large swings in data.
Because E is based on off/sleep/idle power, that’s a lot of extra power being wasted in low power states. This is what an optimized system can take advantage of: better controls for disabling parts of the system that consume power in these low power states. Ideally complete power gating is needed, and given that Raven Ridge was AMD’s latest attempt with a new microarchitecture to go into premium notebooks, OEMs would have taken some serious time and effort to optimize these low power states and maximize both battery life and performance.
Raven Ridge-based Notebooks at IFA 2018
There’s also the added effect of using new APUs, such as the un-announced Ryzen 7 2800H as mentioned above. This has been listed by HP as a 35-54W processor, which is essentially 45W with configurable TDP. Mobile processors are the king of being optimized for idle and sleep power states, so it would not be farfetched to consider that an OEM has optimized both for the chip as they have learned about what it can do as well as given a decent power headroom performance. Add in some good chip binning, and it is fairly simple to see where gains have come from.
The question is all about how much does each change affect the overall score? Moving to a higher powered processor, but with the same CPU/GPU count will account for some 20-30% higher value in the C metric, and if the OEM can claw back that 30% in the lower sleep/idle power states, then put together it would account to close to the 72% value we calculated above.
Adding 30% to C raises the value from 2.47C in RR-2017 to 3.21C in RR-2018. Decreasing power down from 0.44E to 0.33E for a 33% drop means that 3.21C/0.33E = 9.73X.
|AMD's 25x20 Goal: Raven Ridge 2018|
|3DMark 11 P||Compute
|* Data Interpolated from AMD's Graph
** Data predicted that fits with value of X
If we wanted to go in deeper, we’d look to see how the changes would adjust at the Cinebench and 3DM11.
What’s Next for 25x20
We are still two years away from AMD’s self-imposed limit on this goal. Last year, we suggested three ways in which AMD could achieve this goal - a 'same power' goal, a 'half-power' goal, and a 'low-power' goal.
Ryan went the low power route, and suggested that AMD would have to look at a 5W-esque processor in order to get to 25x, which would drop the value of E significantly while keeping the performance of RR-2017. I suggested it would require a bit more performance and power saving. Assuming my numbers are correct for RR-2018, AMD would need to improve performance another 25%, but reduce idle power by half at the same time. Ultimately it would appear that AMD is hoping that next generation 7nm brings either good amount of performance uplift, or idle power is reduced dramatically.
|AMD's 25x20 Goal: Future?|
|3DMark 11 P||Variable C||Variable E||Performance
|* Data Interpolated from AMD's Graph
** Data predicted that fits with value of X
We know that AMD will migrate the APU line onto 7nm next year, which will also include Zen 2 cores. The question about what AMD might have for its APUs by the end of 2020 is a matter for debate, although updates on cores and GPUs are expected as well as process improvements.
We're waiting on AMD to release detailed numbers for its Raven Ridge 2018 system. When we requested them, AMD stated that they didn't have anything extra to announce beyond the graph at the top, but given that the values were listed as Raven Ridge 2018, we expect the data to come by the end of the year.
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DanNeely - Wednesday, September 5, 2018 - link" As reported by our sister website Laptop Mag, the HP Envy x2 with Raven Ridge was a repurposed chassis from HP’s catalogue, rather than something hyper optimized."
I think this sentence is missing a link to a Laptop Mag article.
psxotaku - Wednesday, September 5, 2018 - linkNice article, but I believe the rumored Ryzen 7 2800H and Ryzen 5 2600H are simply based on the Ryzen V1000 embedded series:
Smell This - Wednesday, September 5, 2018 - linkWhat psxotaku said ...
I tend toward low power these days so the embedded 12-watt AMD V1605B w/8 CUs floats my boat. (I hate being pragmatic and responsible.)
RR-2018 brings Vega 11 to the table along with the "Re-spin of Zen." The Internets opine (for years!) that Vega 11 has slightly higher performance at vastly better performance/Watt. Maybe Chipzilla helped to gate those Vega M CCN cores with their "Dynamic Power Sharing." HA!
In the past AMD has typically boosted clocks and efficiencies with new steppings, with no reason to think a second shot would be any different this time around.
iwod - Wednesday, September 5, 2018 - linkRaven Ridge 2018, Zen 2, Vega 2. Lots of good thing coming from AMD.
wumpus - Wednesday, September 5, 2018 - linkI'm curious where the improvements for Raven Ridge 2018 are, I'd assume binning (probably for notebooks).
Zen 2 is taped out for Rome (server chips). No word on Matisse (Ryzen update), Picasso (Raven Ridge update), or Castle Peak (sounds like a threadripper that would almost certainly use either Rome or Matisse chips similar to current threadrippers). As far as I can tell, Rome was "always" (meaning they switched by the time AMD had to worry about how the process effected physical layout of transistors) while the rest may have had work done assuming that GF would manufacture them. Both rework and scheduling time on TSMC fabs may delay things.
Vega 2 won't have many customers, being a professional card in the shadow of nvidia. Machine Learning developers may certainly be interested as well as the traditional CAD users. Vega 2 is also almost certainly the GPU of picasso, so I certainly hope Anandtech gives plenty of coverage to Vega 2 (ignoring how few readers are likely to buy it) and focus more on how well AMD is working with 7nm TSMC and how well vega 2 will work in picasso.
I'm surprised that Navi didn't get a mention. I'd hardly bet on a 2019 debut (unless inside a PS5) but I'd expect it to bring competition to the GPU market. I'd at least expect it to force a 7nm 21x0 line from nvidia sooner than 2080(ti) buyers will expect.
Things to ask AMD:
Is Vega 2 sampling? It should have sampled months ago. Are we going to see it before Jan 1,2019?
Are matisse, picasso, and navi taped out (I'm not so hopeful about navi). AMD typically takes a year from (official) tapeout to launch, so we need to see these things before the year (2018) is out if we expect to see them in 2019 (Q4, don't expect them any earlier). Note that "tapeout" might not be such an important thing for matisse (and to a lesser extent picasso) as they are probably backporting any issues found in Rome and won't officially "tapeout" until the Rome design is finalized.
Targon - Wednesday, September 5, 2018 - linkVega 7nm has been sampling for some time now. A figure of a 40 percent boost to performance over Vega 64 was put out there several months ago. The problem is that Vega is very much tied to HBM2 memory, and due to higher prices/lower availability, AMD is keeping the volume low for that very reason. If HBM2 memory were readily available and the price wasn't as high, then AMD would probably have Vega 7nm out there for gamers at the end of this year.
Ryzen third generation should also be in good shape at this point, but getting yields up at TSMC may be why AMD is not talking about it(to avoid wild speculation that would only hurt the company). Until AMD has at least 300,000 units ready, I don't think AMD wants to put any timeline on when it will officially launch the product. AMD may also be waiting to see what speed Intel i9 chips can actually run at so that AMD can properly price the third generation chips appropriately. If AMD can hit 5GHz on air and Intel can hit 5.3GHz on air, if AMD is able to improve IPC by 10-15 percent, that is the sort of thing AMD will want a big launch event to cover. If AMD can get third generation to the same 5.3GHz on air, that is the sort of thing that AMD management will want to really push.
So, decisions are being made, but until Intel actually ships the new i9 chips, AMD will probably stay silent.
HStewart - Wednesday, September 5, 2018 - linkWhy is that when AMD makes slight changes they call it progress but when Intel makes the changes they call it Marketing or rebranded - they slides here clearly look like Marketing.
FreckledTrout - Wednesday, September 5, 2018 - linkI can explain HStewert. The last few years Intel was not making the best product it can make but AMD is giving it all they have. It's simple as that and everyone that follows tech knows Intel has not put its best product it can make out in the consumer space. In servers sure, but not in the consumer / HEDT segment.
iwod - Thursday, September 6, 2018 - linkExactly this.
Where are the slight changes? I am looking at Skylake, Kaby Lake, Kaby Lake+ , Coffee lake, and I cant remember what lake is it now they are doing.
Than I am looking at Zen and Zen +, and coming Zen 2.
So you thought after all these years Intel has been milking their products, they should have something up their sleeves? No, none at all.
Intel has been marketing their product as a New "Generation". Which is basically redefining what generation means in my dictionary.
Then there is the Intel IGP.
Santoval - Monday, September 10, 2018 - linkWhile Intel has surely procrastinated technologically (largely because they had no competition) one reason that their architecture has been basically frozen since Skylake is that they decided to tie their next architecture (Ice Lake) to their next node, and we all know their problems with their 10nm node. The second generation (10nm+) of their next node actually, since they originally planned to use 10nm for Cannon Lake, which is basically the Skylake design at 10nm plus an AVX-512 block.
Cannon Lake looks like it will remain a beta node, perhaps with only the sole Core-i3 15W CPU with disabled iGPU that was released in low volume. Ice Lake is planned for HVM in mid 2019 and wide release (from top to bottom consumer) in late 2019. On the other hand it appears that they do not have too much confidence in Ice Lake and its successor Tiger Lake, which is why they hired Jim Keller to design Ocean Cove, which is set to be their first post-Core architecture since the original Core CPUs were released in 2006.
The first Ocean Cove CPUs are expected to be released in 2021 at the earliest (~15 years after the original Core was released), either at a late 10nm node or an early 7nm node.