GlobalFoundries this week formally introduced its new custom process technology that will be used to manufacture IBM's z14 CPUs, which in turn were announced earlier this year. The 14HP (14 nm, high performance) tech weds FinFET transistors and SOI substrates to get IBM the best of both worlds: small feature sizes and maximized clockspeed potential.

When IBM and GlobalFoundries agreed to transfer semiconductor manufacturing business of the former to the latter, IBM demanded GF to develop and offer custom fabrication processes for IBM’s server CPUs throughout 2014 to 2024 timeframe and involving multiple nodes. Initially the companies talked about custom 22 nm, 14 nm and 10 nm technologies, but in their final announcement they only mentioned a 10-year exclusive supply agreement without disclosing particular nodes. Therefore, it remains to be seen what GlobalFoundries, which is skipping the 10 nm node, is going to offer to its partner (a custom 7 nm is a natural guess). Earlier this year IBM announced its z14 processors for mainframes and this week GlobalFoundries disclosed details about the process technology used to make these chips.

Before we proceed to 14HP, let’s recap what is the IBM z14 and why the blue giant needed a custom technology to build it. The IBM Z mainframes are designed for 24/7/365 availability with zero downtime and are aimed at mission critical applications like credit card processing. IBM Z mainframes are based on specially designed IBM z-series CPUs, which are unique both in terms of microarchitecture, feature set and even physical layout. Each IBM Z14 blade features six CPUs (which IBM calls CPs) carrying processing cores and L2+L3 caches as well as a system control chip (which IBM calls SC) featuring a large L4 cache as well as various interconnects. Each IBM z14 SC CPU consists of 6.1 billion transistors, runs at 5.2 GHz and contains 10 cores with dedicated 6 MB L2 per core (2MB L2 for instructions, 4MB L2 for data) and 128 MB shared L3. Meanwhile, the system control (SC) chip consists of 9.7 billion transistors and features 672 MB of L4 and interconnects to ensure coherency between CPUs. Needless to say, that both CP and SC are extremely complex and benefit from manufacturing technologies with small feature sizes.

Being very complex and very fast, IBM’s CPUs for z-series mainframes were historically produced using custom fabrication processes that were architected to deliver maximum performance, manufacturing costs be damned. In fact, it was IBM whom first used SOI substrates to build its RS64-IV codenamed ‘Istar’ PowerPC-AS CPUs in 2000, which was then followed by AMD and others whom used SOI to build their own highly-successful processors. The use of SOI enables a tangible increase of CPU clock rates without a massive increase of power consumption, but a SOI wafer substrate costs more than a bulk substrate, so this is exactly what GlobalFoundries’14HP is about.

Comparison of 14 nm Branded Process Technologies
14LPP ?
Fin Pitch ? ? ? ? 42 nm
Gate Pitch ? ? 78 nm 90 nm 70 nm
Min Metal Pitch ? ? 64 nm 64 nm 52 nm
Gate Height ? ? less than 480 nm 480 nm 399 nm
Metal Layers 13 17 13 unknown unknown
Design Library 7.5T 12T 9T 9T unknown

GlobalFoundries says that the 14HP process technology leverages “the proven 14nm FinFET high-volume experience of our Fab 8 facility”, but does not explicitly say that 14HP is based on 14LPP; only that it uses SOI substrates instead of bulk ones. In fact, looking at the numbers it appears to be substantially different. When compared to GF’s 14LPP and similar bulk FinFET process technologies, 14HP can support up to 17 metal layers (vs. 13 for the 14LPP) and uses 12T libraries (vs. 9T and 7.5T for various 14 nodes). As for experience,  14HP will be utilized across the same ASML TWINSCAN NXT scanners that the company uses to produce existing chips using its current FinFET technologies.

GlobalFoundries is not disclosing too many specific details about 14HP, which isn't all that surprising given the situation at hand. There is a single customer that is going to use it, and IBM does not want to share too many details about how it designs its processors as well. So, while we do understand that SOI can help with increasing frequencies and voltages compared to bulk process technologies, we do not have precise numbers here.

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Source: GlobalFoundries

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  • FreckledTrout - Friday, September 22, 2017 - link

    No turbo, that speed is 24x7, should see the cooling on these. We have some in our data center they almost look like they are batman themed server racks.
  • Santoval - Friday, September 22, 2017 - link

    If the pipeline is long enough it can sustain (theoretically*) higher clocks more easily. Intel's Netburst started at 20 pipeline stages (Willamette & Northwood), then reached 31 stages (Prescott, Cedar Mill etc), and there were even plans for successors (Tejas and Jayhawk) with freaking 40 to 50 pipeline stages. These would supposedly reach 7+ Ghz clocks, before they were cancelled and replaced by the Core microarchitecture.
    *Only theoretically apparently. The first samples of Tejas were clocked at merely 2.8 Ghz and had a 150W TDP, much higher than both the previous Prescott and the first Core CPUs that followed.
  • FreckledTrout - Friday, September 22, 2017 - link

    You have to realize these z14's are costing half million and up just for the initial cost. They sell some lower end versions but nobody buys those they just get cheaper servers. In reality most people are likely paying 5 million a year to run these once you account for hardware, software, electricity and your maintenance contracts.
  • Dug - Saturday, September 23, 2017 - link

    Compared to what they bring in on a daily basis it might make sense? I’m actually surprised they have enough customers to make this happen.
  • FunBunny2 - Saturday, September 23, 2017 - link

    -- I’m actually surprised they have enough customers to make this happen.

    it's a symbiotic death spiral. the Fortune 500 adopted mainframes and COBOL ~1960 and kept going for decades. re-writing those billions and billions of lines of code in java or PHP isn't feasible, so IBM's cost to continue to produce mainframes may rise (not necessarily, btw given how much of the guts of z machine have shrunk compared to a 370) which gets passed on to your bank, insurance company, etc.
  • FreckledTrout - Wednesday, September 27, 2017 - link

    People also run Linux partitions like hundreds of Linux VM's on these. That helps offset the costs of buying a mainframe. I find it a novel idea as you migrate apps from old COBOL to java etc you can use extra compute power to run more VM's.
  • DanNeely - Friday, September 22, 2017 - link

    "and uses 12T libraries (vs. 9T and 7.5T for various 14 nodes)"

    This is the second time I've seen a comment about #T libraries in a recent process update article. What exactly does it mean?
  • CajunArson - Friday, September 22, 2017 - link

    I second that comment. There's never been an explanation about what "T" has to do with design libraries (not to mention that different "design libraries" could behave quite differently).
  • MrSpadge - Friday, September 22, 2017 - link

    A lower number means denser designs are possible, so maybe it's the average number of transistors in ... some standard cell mix? I definitely second the explanation request.
  • kaeljae - Friday, September 22, 2017 - link

    This is all over my head but I did find this while googling:

    "The cell height can also be measured by the number of metal tracks that are needed for routing for the cell; in recent nodes we have gone from 12-track (12T), to 9T, to ~7.5T in the latest 14- and 16-nm processes. "

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