Intel Thread Director

One of the biggest criticisms that I’ve levelled at the feet of Intel since it started talking about its hybrid processor architecture designs has been the ability to manage threads in an intelligent way. When you have two cores of different performance and efficiency points, either the processor or the operating system has to be cognizant of what goes where to get the best result from the end-user. This requires doing additional analysis on what is going on with each thread, especially new work that has never been before.

To date, most desktop operating systems operate on the assumption that all cores and the performance of everything in the system is equal.  This changed slightly with simultaneous multithreading (SMT, or in Intel speak, HyperThreading), because now the system had double the threads, and these threads offered anywhere from zero to an extra 100% performance based on the workload. Schedulers were hacked a bit to identify primary and secondary threads on a core and schedule new work on separate cores. In mobile situations, the concept of an Energy Aware Scheduler (EAS) would look at the workload characteristics of a thread and based on the battery life/settings, try and schedule a workload where it made sense, particularly if it was a latency sensitive workload.

Mobile processors with Arm architecture designs have been tackling this topic for over a decade. Modern mobile processors now have three types of core inside – a super high performance core, regular high performance cores, and efficiency cores, normally in a 1+3+4 or 2+4+4 configuration. Each set of cores has its own optimal window for performance and power, and so it relies on the scheduler to absorb as much information as possible to determine the best way to do things.

Such an arrangement is rare in the desktop space - but now with Alder Lake, Intel has an SoC that has SMT performance cores and non-SMT efficient cores. With Alder Lake it gets a bit more complex, and the company has built a technology called Thread Director.

That’s Intel Thread Director. Not Intel Threat Detector, which is what I keep calling it all day, or Intel Threadripper, which I have also heard. Intel will use the acronym ITD or ITDT (Intel Thread Director Technology) in its marketing. Not to be confused with TDT, Intel’s Threat Detection Technology, of course.

Intel Threadripper Thread Director Technology

This new technology is a combined hardware/software solution that Intel has engineered with Microsoft focused on Windows 11. It all boils down to having the right functionality to help the operating system make decisions about where to put threads that require low latency vs threads that require high efficiency but are not time critical.

First you need a software scheduler that knows what it is doing. Intel stated that it has worked extensively with Microsoft to get what they want into Windows 11, and that Microsoft have gone above and beyond what Intel needed. This fundamental change is one reason why Windows 11 exists.

So it’s easy enough (now) to tell an operating system that different types of cores exist. Each one can have a respective performance and efficiency rating, and the operating system can migrate threads around as required. However the difference between Windows 10 and Windows 11 is how much information is available to the scheduler about what is running.

In previous versions of Windows, the scheduler had to rely on analysing the programs on its own, inferring performance requirements of a thread but with no real underlying understanding of what was happening. Windows 11 leverages new technology to understand different performance modes, instruction sets, and it also gets hints about which threads rate higher and which ones are worth demoting if a higher priority thread needs the performance.

Intel classifies the performance levels on Alder Lake in the following order:

  1. One thread per core on P-cores
  2. Only thread on E-cores
  3. SMT threads on P-cores

That means the system will load up one thread per P-core and all the E-cores before moving to the hyperthreads on the P-cores.

Intel’s Thread Director controller puts an embedded microcontroller inside the processor such that it can monitor what each thread is doing and what it needs out of its performance metrics. It will look at the ratio of loads, stores, branches, average memory access times, patterns, and types of instructions. It then provides suggested hints back to the Windows 11 OS scheduler about what the thread is doing, whether it is important or not, and it is up to the OS scheduler to combine that with other information about the system as to where that thread should go. Ultimately the OS is both topologically aware and now workload aware to a much higher degree.

Inside the microcontroller as part of Thread Director, it monitors which instructions are power hungry, such as AVX-VNNI (for machine learning) or other AVX2 commands that often draw high power, and put a big flag on those for the OS for prioritization. It also looks at other threads in the system and if a thread needs to be demoted, either due to not having enough free P-cores or for power/thermal reasons, it will give hints to the OS as to which thread is best to move. Intel states that it can profile a thread in as little as 30 microseconds, whereas a traditional OS scheduler may take 100s of milliseconds to make the same conclusion (or the wrong one).

On top of this, Intel says that Thread Director can also optimize for frequency. If a thread is limited in a way other than frequency, it can detect this and reduce frequency, voltage, and power. This will help the mobile processors, and when asked Intel stated that it can change frequency now in microseconds rather than milliseconds.

We asked Intel about where an initial thread will go before the scheduling kicks in. I was told that a thread will initially get scheduled on a P-core unless they are full, then it goes to an E-core until the scheduler determines what the thread needs, then the OS can be guided to upgrade the thread. In power limited scenarios, such as being on battery, a thread may start on the E-core anyway even if the P-cores are free.

For users looking for more information about Thread Director on a technical, I suggest reading this document and going to page 185, reading about EHFI – Enhanced Hardware Frequency Interface. It outlines the different classes of performance as part of the hardware part of Thread Director.

It’s important to understand that for the desktop processor with 8 P-cores and 8 E-cores, if there was a 16-thread workload then it will be scheduled across all 8 P-cores with 8 threads, then all 8 E-cores with the other 8 threads. This affords more performance than enabling the hyperthreads on the P-cores, and so software that compares thread-to-thread loading (such as the latest 3DMark CPU Profile test) may be testing something different compared to processors without E-cores.

On the question of Linux, Intel only went as far to say that Windows 11 was the priority, and they’re working upstreaming a variety of features in the Linux kernel but it will take time. An Intel spokesperson said more details closer to product launch, however these things will take a while, perhaps months and years, to get to a state that could be feature-parity equivalent with Windows 11.

One of the biggest questions users will ask is about the difference in performance or battery between Windows 10 and Windows 11. Windows 10 does not get Thread Director, but relies on a more basic version of Intel’s Hardware Guided Scheduling (HGS). In our conversations with Intel, they were cagy to put any exact performance differential metrics between the two, however based on understanding of the technology, we should expect to see better frequency efficiency in Windows 11. Intel stated that even though the new technology in Windows 11 will mean threads will move more often than in Windows 10, potentially adding latency, in their testing it wasn’t in any way human perceivable. Ultimately because the Win11 configuration can also optimize for power and efficiency, especially in mobile, Intel puts the win on Windows 11.

The only question is if Windows 11 will launch in time for Alder Lake.

Alder Lake: Intel 12th Gen Core Golden Cove Microarchitecture (P-Core) Examined
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  • abufrejoval - Saturday, August 21, 2021 - link

    Since AVX-512 isn't new, I'm somewhat doubtful on the bug theory.

    And since Intel doesn't do chiplets yet, they can't be reusing that silicon for server CPUs either.

    It really has me think that the AVX-512 guys tried to push their baby through into production until the bloody final battle, when the E/P-Core symmetry team shut them down (for now, it's all fuses, right?).

    It's really very much a matter of how you want to use these resources and educating both operating systems and users about their potential and limitations. If all you see in E-cores is a way to run a P-core task on less energy budget, that symmetry is critical. If you see E-cores as an add-on resource that somewhat functionally limited (but might have better side-channel resilience or run special purpose VMs etc.), yet available for low silicon real-estate, it's another story.

    On notebooks on batteries, the symmetric view wins out. For anything on a powerline, the E-cores may make some sense as functionally constrained extra resources, I can't see the power savings vs. good idle there (well, perhaps a single E-core, like the Tegra 3 had against it's quad P-cores).

    It's very hard to maintain real flexibility when things get baked into silicon.

    I'd say product managers got the better over the engineers and what you get is a compromise, which hardly ever ideal nor easy to understand without the context of its creation.
  • mode_13h - Sunday, August 22, 2021 - link

    > It really has me think that the AVX-512 guys tried to push their baby through into
    > production until the bloody final battle,

    That doesn't explain the backport of VNNI to AVX2, unless that was already being done for other reasons.

    Intel went through this once, already, with Lakefield. That was like 2 years ago, and forced the same situation of the P-core being kneecapped. So, this thing can't have been a surprise.

    Now, wouldn't it be cool if BIOS gave you a choice between enabling the E-cores and having AVX-512 on the P-cores? I know it'd create more headaches for the customer support teams at Intel and many OEMs, but that would at least be a more customer-centric way to make the tradeoff.
  • Spunjji - Tuesday, August 24, 2021 - link

    Giving customers more choice for no additional cost is not the Intel way!
  • Oxford Guy - Thursday, August 26, 2021 - link

    Some here fervently believe enthusiasts who build their own PCs aren’t going to enter BIOS to turn on XMP...
  • Spunjji - Friday, August 27, 2021 - link

    @Oxford Guy - only ever seen people argue the majority of users won't do that, not enthusiasts specifically.
  • SystemsBuilder - Friday, August 20, 2021 - link

    Breaking out VNNI from AVX512 and keeping it in Alder Lake is to accelerate Neural Net inference. Many other parts of AVX512 (i.e. AVX512F etc) are necessary to sufficiently accelerate NN learning.
    Intel probably thought that Alder Lake CPUs would only be used in inference scenarios and therefor reserved AVX512 and AMX to Sapphire rapids server, workstation and hopefully the HEDT platform road maps.

    Intel forgot (or more likely did not care) that companies have, after 5 years of AVX512 with implementations as far down into the consumer stack as Ice Lake and Tiger Lake lap tops, tuned libraries to take advantage of AVX512 in OTHER scenarios than deep learning. Those libraries are now going to be regressing to AVX2 when run on Alder lake CPUs, effectively knee capped, executed on P and crap cores, ops sorry, meant E cores.
  • mode_13h - Saturday, August 21, 2021 - link

    To be fair, I think Intel had further motives for porting VNNI to AVX2. They sell Atom processors into applications where inferencing is a useful capability. Skylake CPUs are already pretty good at inferencing, with just baseline AVX2, so VNNI can only help.

    Still, the situation is something of an own-goal. I'll bet Intel will be nursing that wound for the next few years. I don't expect they'll make the same decision/mistake in Raptor Lake.
  • StoykovK - Friday, August 20, 2021 - link

    Intel stated that ADL has 6 decoders from 4, but didn't Skylake has 5 (4 simple + 1 complex)?

    I'm a little bit confused. It looks like, from architecture point, Golden Cove compared to WillowCove is bigger update, than WillowCove to SkyLake, but both result ~20% IPC.

    E-cores: Really good idea to get high score in multi-core benchmarks. GoldenCove looks like ~33% faster than E-cores, but taking a lot more power. Does anybody have an idea how wide is E-cores AVX- 128bit or 256bit.
  • TristanSDX - Friday, August 20, 2021 - link

    SSE - 128 bit, AVX - 256 bit, AVX-512 - 512 bit
  • StoykovK - Friday, August 20, 2021 - link

    Zen/Zen+, Sandy Bridge, Ivy Bridge fuses 2x128bit units in order to execute single 256bit AVX.

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