The Cortex-A710: More Performance with More Efficiency

While the Cortex-X2 goes for all-out performance while paying the power and area penalties, Arm's Cortex-A710 design goes for a more efficient approach.

First of all, the new product nomenclature now is self-evident in regards to what Arm will be doing going forward- they’re skipping the A79 designation and simply starting fresh with a new three-digit scheme with the A710. Not very important in the grand scheme of things but an interesting marketing tidbit.

The Cortex-A710, much like the X2, is an Armv9 core with all new features that come with the new architecture version. Unlike the X2, the A710 also supports EL0 AArch32 execution, and as mentioned in the intro, this was mostly a design choice demanded by customers in the Chinese market where the ecosystem is still slightly lagging behind in moving all applications over to AArch64.

In terms of front-end enhancements, we’re seeing the same branch prediction improvements as on the X2, with larger structures as well as better accuracy. Other structures such as the L1I TLB have also seen an increase from 32 entries to 48 entries. Other front-end structures such as the macro-OP cache remain the same at 1.5K entries (The X2 also remains at 3K entries).

A very interesting choice for the A710 mid-core is that Arm has reduced the macro-OP cache and dispatch stage throughputs from 6-wide to 5-wide. This was mainly a targeted power and efficiency optimization for this generation, as we’re seeing a more important divergence between the Cortex-A and Cortex-X cores in terms of their specializations and targeted use-cases for performance and power.

The dispatch stage also features the same optimizations as on the X2, removing 1 cycle from the pipeline towards an overall 10-cycle pipeline design.

Arm also focuses on core improvements that affect the uncore parts of the system, which take place thanks to the new improvements in the prefetcher designs and how they interact with the new DSU-110 (which we’ll cover later). The new combination of core and DSU are able to reduce access from the core towards the L3 cache, as well as reducing the costly DRAM accesses thanks to the more efficiency prefetchers and larger L3 cache.

In terms of IPC, Arm advertises +10%, but again the issue with this figure here is that we’re comparing an 8MB L3 cache design to a 4MB L3 cache design. While this is a likely comparison for flagship SoCs next year, because the Cortex-A710 is also a core that would be used in mid-range or lower-end SoCs which might use much smaller L3 caches, it’s unlikely we’ll be seeing such IPC improvements in that sector unless the actual SoCs really do also improve their DSU sizes.

More important than the +10% improvement in performance is that, when backing off slightly in frequency, we can see that the power reduction can be rather large. According to Arm, at iso-performance the A710 consumes up to 30% less power than the Cortex-A78. This is something that would greatly help with sustained performance and power efficiency of more modestly clocked “middle” core implementations of the Cortex-A710.

In general, both the X2 and the A710’s performance and power figures are quite modest, making them the smallest generation-over-generation figures we’ve seen from Arm in quite a few years. Arm explains that due to this generation having made larger architectural changes with the move to Armv9, there has been an impact in regards to the usual efficiency and performance improvements that we’ve seen in prior generations.

Both the X2 and the A710 are also the fourth generation of this Austin microarchitecture family, so we’re hitting a wall of diminishing returns and maturity of the design. A few years ago we were under impression that the Austin family would only go on for three generations before handing things over to a new clean-sheet design from the Sophia team, but that original roadmap has been changed, and now we'll be seeing the new Sophia core with larger leaps in performance being disclosed next year.

The Cortex-X2: More Performance, Deeper OoO The Cortex-A510: Brand-new Little Design Comes in Pairs
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  • dotjaz - Wednesday, May 26, 2021 - link

    Where do you even get expensive 32bit phones? There is no REAL shift other than Play Store policy which doesn't even affect end users. Reply
  • mode_13h - Wednesday, May 26, 2021 - link

    Look up you phone specs on a site like gsmarena and see what cores it has. If any are ARM Cortex-A35, A5x, or A7x, then you already have a 64-bit phone.

    Most phones sold for the past 5 years have been 64-bit.
    Reply
  • RSAUser - Wednesday, May 26, 2021 - link

    Anything launched with lollipop or higher is most probably 64bit, so shouldn't be an issue. Reply
  • SarahKerrigan - Tuesday, May 25, 2021 - link

    A55, But Wider And More Dozery was not what I expected.

    Still, it looks quite decent. Excited to see A710 and A510 in silicon. Not sure how to feel about X2.

    The fun begins immediately! Or in about seven months, as the case may be!
    Reply
  • eastcoast_pete - Tuesday, May 25, 2021 - link

    I had a somewhat different reaction: the X2 makes some sense, it's a continuation of the X1 performance over efficiency approach, the 710 is the next big "A" core, and the 510 is, as Andrei wrote, a bit underwhelming. To me, it looks like ARM didn't even consider using their A65 design (OOO) and come up with a true contender for the perf/W crown for efficiency cores. Apple remains light years ahead here, and anyone in the non-iOS space is stuck with this attempt to inject some Bulldozer design features into the tired in-order A55 lineage. With no custom ARM-derived cores on the horizon (doubt if Google will surprise us with their custom SoC), what's next? RISC-V? Reply
  • SarahKerrigan - Tuesday, May 25, 2021 - link

    No custom cores on the horizon? What about Nuvia and Ampere's cores? Reply
  • mode_13h - Tuesday, May 25, 2021 - link

    There remains the outside possibility that AMD or Intel decides to enter the ARM race. Reply
  • ikjadoon - Tuesday, May 25, 2021 - link

    I will not yet forgive AMD for binning Jim Keller's K12 design. Qualcomm, Arm, Apple all needed more competition in the perf-watt battle. Reply
  • mode_13h - Tuesday, May 25, 2021 - link

    > I will not yet forgive AMD for binning Jim Keller's K12 design.

    It costs money to bring a chip to market, and AMD was deep in debt. Lisa Su barely managed to keep the lights on, with that Chinese licensing deal. And the market for ARM servers just wasn't ripe.

    Assuming they really couldn't afford to do both (at least, without significant compromises), they definitely made the right call by going with x86.
    Reply
  • mode_13h - Tuesday, May 25, 2021 - link

    BTW, I agree that I'd love to see how well it compared to other ARM cores of its day, but we can't ignore the practical and business realities.

    I hope AMD will one day reveal more about the K12. That definitely won't happen as long as a potential successor is in the works!
    Reply

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