Russia’s Elbrus 8CB Microarchitecture: 8-core VLIW on TSMC 28nmby Dr. Ian Cutress on June 1, 2020 8:00 AM EST
All of the world’s major superpowers have a vested interest in building their own custom silicon processors. The vital ingredient to this allows the superpower to wean itself off of US-based processors, guarantee there are no supplemental backdoors, and if needed add their own. As we have seen with China, custom chip designs, x86-based joint ventures, or Arm derivatives seem to be the order of the day. So in comes Russia, with its custom Elbrus VLIW design that seems to have its roots in SPARC.
Russia has been creating processors called Elbrus for a number of years now. For those of us outside Russia, it has mostly been a big question mark as to what is actually under the hood – these chips are built for custom servers and office PCs, often at the direction of the Russian government and its requirements. We have had glimpses of the design, thanks to documents from Russian supercomputing events, however these are a few years old now. If you are not in Russia, you are unlikely to ever get your hands on one at any rate. However, it recently came to our attention of a new programming guide listed online for the latest Elbrus-8CB processor designs.
The latest Elbrus-8CB chip, as detailed in the new online programming guide published this week, built on TSMC’s 28nm, is a 333 mm2 design featuring 8 cores at 1.5 GHz. Peak throughput according to the documents states 576 GFLOPs of single precision, with the chip offering four channels of DDR4-2400, good for 68.3 GB/s. The L1 and L2 caches are private, with a 64 kB L1-D cache, a 128 kB L1-I cache, and a 512 kB L2 cache. The L3 cache is shared between the cores, at 2 MB/core for a total of 16 MB. The processor also supports 4-way server multiprocessor combinations, although it does not say on what protocol or what bandwidth.
It is a compiler focused design, much like some other complex chips, in that most of the optimizations happen at the compiler level. Based on compiler first designs in the past, that typically does not make for a successful product. Documents from 2015 state that a continuing goal of the Elbrus design is x86 and x86-64 binary translation with only a 20% overhead, allowing full support for x86 code as well as x86 operating systems, including Windows 7 (this may have been updated since 2015).
The core has six execution ports, with many ports being multi-capable. For example, four of the ports can be load ports, and two of the ports can be store ports, but all of them can do integer operations and most can do floating point operations. Four of the ports can do comparison operations, and those four ports can also do vector compute.
This short news post is not meant to be a complete breakdown of the Elbrus capabilities – we have amusingly joked internally at what frequency a Cortex X1 with x86 translation would match the capabilities of the 8-core Elbrus, however users who want to get to grips with the design can open and read the documentation at the following address:
The bigger question is going to be how likely any of these state-funded processor development projects are going to succeed at scale. State-funded groups should, theoretically, be the best funded, however even with all the money in the world, engineers are still required to get things done. Even if there ends up being a new super-CPU for a given superpower, there will always be vested interests in an amount of security though obscurity, especially if the hardware is designed specifically to cater to state-secret levels of compute. There's also the added complication of the US government tightening its screws around TSMC and ASML to not accept orders from specific companies - any plans to expand those boundaries could occur, depending how good the products are or how threatened some nations involved feel.
Source: Blu (Twitter)
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brucethemoose - Monday, June 1, 2020 - linkSMIC is making some huge strides. I don't think they'll ever overtake western fabs, but the gap is closing pretty quickly.
mode_13h - Monday, June 1, 2020 - linkNo doubt, but how much did it cost to get there? Do you think Russia has that kind of $$$ to throw at the problem, especially when sanctions continue to take their toll?
bagamut - Tuesday, June 2, 2020 - linkRussia has that kind of $$$, much more than Saudis, and ~5th economic in the world to support that, but there is no urgent need to do that now. Semiconductor industry for military and aerospace applications exists and works. Competition with mass production semi is not possible, cuz this is all regulated by politics. China is an example of that.
FunBunny2 - Tuesday, June 2, 2020 - link"Russia has that kind of $$$"
whaaaaaaa?? Russia's GDP is minuscule: no better 11th globally. New York, Texas, and California are bigger.
mshigorin - Monday, June 1, 2020 - linkWe use to deliver asymmetric solutions to problems at hand. For one, there's an interesting development in... well, let it stay interesting for a while ;-)
nolem - Sunday, September 4, 2022 - linkBesides the point, that all semiconductor comapies in russia aree now again working like in the soviet era. They never were able to build something in 10 years tech delays to the west. The only way was to exploit the techs from the states of the Warsaw Pact like the gdr resources until 1989. Therefore i totally agree. They will never be able under this goverment to develop anything beyond 5 years tech delay to the current government. This is rediculous.
mode_13h - Monday, June 1, 2020 - linkIA64 didn't have SIMD instructions. However, if remained a going concern for long enough, they could've added them.
mode_13h - Monday, June 1, 2020 - linkIt's funny how many IA64 "experts" there are, on here.
The only person I've seen that seems to *actually* know anything about IA64 is @SarahKerigan.
azfacea - Monday, June 1, 2020 - linkand here we go. the predictable smug *expert* who shows up to educate us, who actually happens to be as clueless as smug they are. but if I were expose you and use some of your own smugness, then you'd start ramping up accusations of rudeness and toxicity. thats the ultimate guaranteed outcome of such threads. I wont play your game and i think i am done here with this thread.
i never said IA64 mr *expert* which is an ISA, i said VLIW. i was referring to the trend of shifting logic from the CPU to the compiler that failed to achieve its goals, precisely for the reasons i mentioned. ... now here we go, i am not doing it ... go talk to the other experts in this thread.
mode_13h - Monday, June 1, 2020 - linkNotice that I didn't call myself an expert, but at least I know more than the 1 or 2 bullet points you seem to have latched onto.
Instead of trying to tear me down, why don't you read up, yourself. Then you can actually be somewhat educated on the matter, next time.
How is it fair to pre-accuse me of playing the "toxicity and rudeness" card? That's not my M.O. I try to focus on the merits of a post. It's only those without merit that take cheap shots.
Speaking of merits:
>>> intel/hp and others squandered tens of billions on VLIW and eventually came accept their fate.
> i never said IA64 mr *expert* which is an ISA
You clearly implied that IA64 was VLIW, which it's not. EPIC was about working around the limitations of VLIW, including those you cited. To that end, it *seems* that this chip from Elbrus is even further behind.