Intel has recently updated its developer documentation for instruction set extensions, and in the process has disclosed information on both new instructions for and the codename of its next-generation low-power processor microarchitecture. Dubbed "Tremont", the forthcoming processor core look to replace Goldmont Plus in the upcoming Atom, Celeron, and Pentium Silver-branded SoCs.

According to the Intel Architecture Instruction Set Extensions (ISE) and Future Features Programming Reference document, the Goldmont Plus microarchitecture will not be the end of the road for Intel’s low-cost/low-power cores. In the coming years it will be succeeded by the codenamed Tremont microarchitecture and its successors. On the manufacturing side of matters, nothing has officially been disclosed, but right now our suspicion is that processors based on the Tremont will be made using the company’s 10 nm process technology. To date we haven't seen Intel use their enhanced “+” and “++” 14nm process technologies to make SoCs for entry-level and energy-efficient PCs - as the original 14nm provides better density - so it seems unlikely that Intel would start now.

A key question about the Tremont is what architecturaly improvements it will bring. While Intel's document does specify the new instructions, it doesn't offer any general architectural insight. Intel's general trend thus far since Silvermont has been to gradually widen their out-of-order execution design, starting with two-way, moving to three-way (Goldmont), and then to a three-way front-end plus a four-way allocation and retirement backend. So it may be that we see Intel go this route, as they already have a number of tricks left in their bag from Core, and it meshes well with the high density aspects of their 10nm processes, which favors more complex processors.

As for the ISE improvements, Intel’s Tremont will feature CLWB, GFNI (SSE-based), ENCLV, and Split Lock Detection instruction set extensions, which are also set to arrive with Intel’s Ice Lake processors. Also set to arrive with Tremont will be CLDEMOTE, direct store, and user wait instructions (see details in the table below). Unlike the earlier instructions, these are unique to Tremont and are not scheduled to be supported by the Ice Lake (or other documented Intel’s cores).

New Instruction Set Extensions of Goldmont Plus and Tremont CPUs
  Instruction Purpose Description
Goldmont Plus PTWRITE

Write Data to a Processor Trace Packet
Debugging Unclear.

User-Mode Instruction Prevention
Security Prevents execution of certain instructions if the Current Privilege Level (CPL) is greater than 0. If these instructions were executed while in CPL > 0, user space applications could have access to system-wide settings such as the global and local descriptor tables, the task register and the interrupt descriptor table.

Read Processor ID
General Quickly reads processor ID to discover its feature set and apply optimizations/use specific code path if possible.
Tremont CLWB

Cache Line
Write Back
Performance Writes back modified data of a cache line similar to CLFLUSHOPT, but avoids invalidating the line from the cache (and instead transitions the line to non-modified state). CLWB attempts to minimize the compulsory cache miss if the same data is accessed temporally after the line is flushed if the same data is accessed temporally after the line is flushed.
GFNI (SSE) Security SSE-based acceleration of Galois Field Affine Transformation alghorithms.
ENCLV Security Further enhancement of SGX version 1 capabilities.
CLDEMOTE Performance Enables CPU to demote a cache line with a specific adress from the nearest cache to a more distant cache without writing back to memory. Speeds up access to this line by other cores within a CPU.
Direct stores: MOVDIRI, MOVDIR64B Performance  
User wait: TPAUSE, UMONITOR, UMWAIT Power Direct CPU to enter certain stages before an event happens.
Split Lock Detection    
Source: Intel Architecture Instruction Set Extensions and Future Features Programming Reference (pages 12 and 13)

The fact that Intel is readying its “Future Tremont and later” microarchitectures reveals that even after the company withdrew from smartphone SoCs, it sees plenty of applications that could use its low-power/low-cost Atom cores. There is sitll a notable market for budget PCs as well as embedded and semi-embeded markets for items like IoT edge devices, all of which Intel intends to continue serving with the line of smaller, cheaper cores. Meanwhile, consistent ILP and performance improvements as well as introduction of new ISEs to these microarchitectures show that Intel wants these cores to offer competitive performance to other low-cost processors, while still maintaining near feature set parity to Intel's high-performance cores.

Related Reading

Sources: Intel, WikiChip

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  • Wardrive86 - Monday, April 23, 2018 - link

    8 core A53s outperform most quad "big cores" from yesteryear. Snapdragon 625 for example, same single thread performance as the A15/Krait based SoCs, double the multithread performance, at a fraction of the cost.
  • patrickjp93 - Monday, April 23, 2018 - link

    Uh, no. Geekbench is lying to you on that one. When Geekbench starts treating x86 as a first class citizen and doesn't withhold AVX/2/512 optimisations when it has all of the ARM Neon ones, you'll see the world how it really is.
  • Wilco1 - Tuesday, April 24, 2018 - link

    Stop spreading lies. Geekbench supports x86 as a first class and optimizes for AVX2 and FMA. See for proof. The truth is x86 is running out of steam.
  • Wardrive86 - Tuesday, April 24, 2018 - link

    I wasn't referring to just Geekbench but a multitude of other benchmarks, emulators and real world experience. Also I never said anything about x86, I was merely defending the ARM 8 core .little philosophy which does in fact make sense
  • StevoLincolnite - Monday, April 23, 2018 - link

    Nah. Bugger the BIG.little.
    Just have aggressive turbo states, so when cores are being underutilized... Funnel the TDP into boosting a few remaining cores.
  • HStewart - Monday, April 23, 2018 - link

    There is actually a 16 core Atom server chip - it would be cool to see it 2in1 but they lack some Core chip functionality
  • mode_13h - Tuesday, April 24, 2018 - link

    Not a minor point is that it burns too much power for such applications.
  • rahvin - Tuesday, April 24, 2018 - link

    There are already 16 core atoms, the C3000 chips that make up the Atom Server chips.
  • serendip - Monday, April 23, 2018 - link

    Atom is dead and gone unless Intel can get Atom tablets selling again. I'm crazy enough to use a Cherry Trail Windows tablet as my main travel machine, it's fine for what it does and the battery life is excellent. It really is too bad that Intel dropped out of the 2W TDP segment.
  • patrickjp93 - Monday, April 23, 2018 - link

    ??? How about dumb terminals for Citrix in big corporations? Thousands of Atoms get sold for that purpose.

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