Intel has recently updated its developer documentation for instruction set extensions, and in the process has disclosed information on both new instructions for and the codename of its next-generation low-power processor microarchitecture. Dubbed "Tremont", the forthcoming processor core look to replace Goldmont Plus in the upcoming Atom, Celeron, and Pentium Silver-branded SoCs.

According to the Intel Architecture Instruction Set Extensions (ISE) and Future Features Programming Reference document, the Goldmont Plus microarchitecture will not be the end of the road for Intel’s low-cost/low-power cores. In the coming years it will be succeeded by the codenamed Tremont microarchitecture and its successors. On the manufacturing side of matters, nothing has officially been disclosed, but right now our suspicion is that processors based on the Tremont will be made using the company’s 10 nm process technology. To date we haven't seen Intel use their enhanced “+” and “++” 14nm process technologies to make SoCs for entry-level and energy-efficient PCs - as the original 14nm provides better density - so it seems unlikely that Intel would start now.

A key question about the Tremont is what architecturaly improvements it will bring. While Intel's document does specify the new instructions, it doesn't offer any general architectural insight. Intel's general trend thus far since Silvermont has been to gradually widen their out-of-order execution design, starting with two-way, moving to three-way (Goldmont), and then to a three-way front-end plus a four-way allocation and retirement backend. So it may be that we see Intel go this route, as they already have a number of tricks left in their bag from Core, and it meshes well with the high density aspects of their 10nm processes, which favors more complex processors.

As for the ISE improvements, Intel’s Tremont will feature CLWB, GFNI (SSE-based), ENCLV, and Split Lock Detection instruction set extensions, which are also set to arrive with Intel’s Ice Lake processors. Also set to arrive with Tremont will be CLDEMOTE, direct store, and user wait instructions (see details in the table below). Unlike the earlier instructions, these are unique to Tremont and are not scheduled to be supported by the Ice Lake (or other documented Intel’s cores).

New Instruction Set Extensions of Goldmont Plus and Tremont CPUs
  Instruction Purpose Description
Goldmont Plus PTWRITE

Write Data to a Processor Trace Packet
Debugging Unclear.

User-Mode Instruction Prevention
Security Prevents execution of certain instructions if the Current Privilege Level (CPL) is greater than 0. If these instructions were executed while in CPL > 0, user space applications could have access to system-wide settings such as the global and local descriptor tables, the task register and the interrupt descriptor table.

Read Processor ID
General Quickly reads processor ID to discover its feature set and apply optimizations/use specific code path if possible.
Tremont CLWB

Cache Line
Write Back
Performance Writes back modified data of a cache line similar to CLFLUSHOPT, but avoids invalidating the line from the cache (and instead transitions the line to non-modified state). CLWB attempts to minimize the compulsory cache miss if the same data is accessed temporally after the line is flushed if the same data is accessed temporally after the line is flushed.
GFNI (SSE) Security SSE-based acceleration of Galois Field Affine Transformation alghorithms.
ENCLV Security Further enhancement of SGX version 1 capabilities.
CLDEMOTE Performance Enables CPU to demote a cache line with a specific adress from the nearest cache to a more distant cache without writing back to memory. Speeds up access to this line by other cores within a CPU.
Direct stores: MOVDIRI, MOVDIR64B Performance  
User wait: TPAUSE, UMONITOR, UMWAIT Power Direct CPU to enter certain stages before an event happens.
Split Lock Detection    
Source: Intel Architecture Instruction Set Extensions and Future Features Programming Reference (pages 12 and 13)

The fact that Intel is readying its “Future Tremont and later” microarchitectures reveals that even after the company withdrew from smartphone SoCs, it sees plenty of applications that could use its low-power/low-cost Atom cores. There is sitll a notable market for budget PCs as well as embedded and semi-embeded markets for items like IoT edge devices, all of which Intel intends to continue serving with the line of smaller, cheaper cores. Meanwhile, consistent ILP and performance improvements as well as introduction of new ISEs to these microarchitectures show that Intel wants these cores to offer competitive performance to other low-cost processors, while still maintaining near feature set parity to Intel's high-performance cores.

Related Reading

Sources: Intel, WikiChip

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  • Wilco1 - Monday, April 23, 2018 - link

    Atom with AVX512, aren't those all cancelled? I think the Phi's were the only CPUs where use of AVX2 or AVX512 doesn't cause a large slowdown of all cores. It's not a great thing if you have to actively avoid using AVX512 to get best performance...
  • HStewart - Monday, April 23, 2018 - link

    Well the stories of Atom's cancel must be internet lies - there is a lot of that going around especially when one is on top.

    On AVX512 it has a special need - AVX512 is new and it more likely that true performance comes when application uses AVX512 efficiently
  • Wilco1 - Tuesday, April 24, 2018 - link

    Well at lot of Atoms have been cancelled which doesn't suggest at all it is on top.

    The big issue with AVX512 is exactly that it is too inefficient, using way too much power, and that impacts performance quite badly. So a lot of software doesn't use AVX512 to avoid this slowdown.

    Note even minor use of AVX512 can reduce performance significantly:
  • HStewart - Tuesday, April 24, 2018 - link

    I think a lot of software does not use AVX512 - because it so specialize and new - for what it does is significant - but of course if enabled it likely slow normal x86 operations down

    I not sure how reliable your link is - others seem to discredit the information
  • Wilco1 - Tuesday, April 24, 2018 - link

    It's a well-known fact that clock frequency goes down by a few hundred MHz whenever you use AVX2 or AVX512 even for a few instructions - and this slowdown lasts for long after the last use of such instructions.
  • mode_13h - Monday, April 23, 2018 - link

    Where was it ever reported to appear outside of a Xeon Phi? I've never read such.

    The cores in Xeon Phi are always customized to the application. The Silvermonts which had AVX512 also had 4-way hyperthreading (of which normal Silvermont has none).
  • Wilco1 - Tuesday, April 24, 2018 - link

    Indeed, Xeon Phi uses an Atom derivative, and all new generations have been cancelled. See eg.
  • Elstar - Tuesday, April 24, 2018 - link

    Phi isn't dead. They just changed plans. "Knights Hill" is dead, long live "Knights Crest"
  • Alistair - Monday, April 23, 2018 - link

    People don't like Atom because it actually costs Intel almost nothing to manufacture a dual core i3 instead. Atom wouldn't exist anywhere, even in the low cost market, if Intel didn't want obscene margins. You don't need that kind of power efficiency in the laptop market for example.
  • HStewart - Monday, April 23, 2018 - link

    One thing one forgets is that the atom is SOC and with i3 it takes addition chips to make the system, but as technology increases higher end models incorporate more of system - in fact the laptop I am typing this has 4.1Ghz quad core i7 with 20 Unit Vega GPU and 4G of HDM2 memory on a custom die. I believe EMIB will be the future.

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